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DTSTAMP:20250822T115806Z
LOCATION:Room 5.2D02
DTSTART;TZID=Europe/Stockholm:20250618T140000
DTEND;TZID=Europe/Stockholm:20250618T143000
UID:submissions.pasc-conference.org_PASC25_sess103_msa127@linklings.com
SUMMARY:Celerity - SYCL-Based High-Productivity Development at HPC Scale
DESCRIPTION:Peter Thoman (University of Innsbruck)\n\nThe vendor-agnostic 
 SYCL standard provides a C++-based foundation for the development of appli
 cations targeting heterogeneous systems. However, while SYCL supports mult
 iple devices in a single shared memory host system or node, leveraging thi
 s support requires developers to manually take care of the issues of work 
 splitting and data coherence across devices. Developing for an HPC environ
 ment, which features a large number of accelerators in a distributed memor
 y cluster, is even more challenging and labor-intensive. As a consequence,
  algorithmic decisions are often difficult to change once taken, reducing 
 the potential for experimenting with different approaches at scale.\nThis 
 talk will briefly introduce a subset of SYCL, and demonstrate how the Cele
 rity runtime system extends the applicability of single-GPU concepts to cl
 usters, in a manner largely transparent to the programmer. The applicabili
 ty of this system, and its potential for enabling the rapid evaluation of 
 different implementation choices, will be illustrated with scalability stu
 dies on a set of real-world use cases. Additionally, some SYCL software en
 gineering best practices based on the Celerity development experience will
  be shared.\n\nDomain: Engineering, Computational Methods and Applied Math
 ematics\n\nSession Chair: Andrey Alekseenko (KTH Royal Institute of Techno
 logy, PDC Center for High Performance Computing)\n\n
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