BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:Europe/Stockholm
X-LIC-LOCATION:Europe/Stockholm
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=-1SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=-1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20250822T115809Z
LOCATION:Room 5.2D02
DTSTART;TZID=Europe/Stockholm:20250616T153000
DTEND;TZID=Europe/Stockholm:20250616T160000
UID:submissions.pasc-conference.org_PASC25_sess132_msa124@linklings.com
SUMMARY:Deep Neural Network Inference with Analog In-Memory Computing
DESCRIPTION:Manuel Le Gallo (IBM Research Europe)\n\nThe need to repeatedl
 y shuttle around synaptic weight values from memory to processing units ha
 s been a key source of energy inefficiency associated with hardware implem
 entation of artificial neural networks. Analog in-memory computing (AIMC) 
 with spatially instantiated synaptic weights holds high promise to overcom
 e this challenge, by performing matrix-vector multiplications directly wit
 hin the network weights stored on a chip to execute an inference workload.
  In this talk, I will first present our latest multi-core AIMC chip in 14-
 nm complementary metal–oxide–semiconductor (CMOS) technology with backend-
 integrated phase-change memory (PCM). The fully-integrated chip features 6
 4 256x256 AIMC cores interconnected via an on-chip communication network. 
 Experimental inference results on ResNet and LSTM networks will be present
 ed, with all the computations associated with the weight layers and the ac
 tivation functions implemented on-chip. Then, I will present our open-sour
 ce toolkit (https://aihw-composer.draco.res.ibm.com/) to simulate inferenc
 e and training of neural networks with AIMC. Finally, I will present our l
 atest architectural solutions to increase the weight capacity of AIMC chip
 s towards supporting large-language models, as well as alternative solutio
 ns suited for low-power edge computing applications.\n\nDomain: Engineerin
 g\n\nSession Chairs: Mauro Bianco (ETH Zurich / CSCS, ETH Zurich) and Nur 
 Aiman Fadel (ETH Zurich / CSCS)\n\n
END:VEVENT
END:VCALENDAR